23.09.2026: The Wednesday Webinar Series: #9 Advanced Interconnects and Packaging for GaN
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Although GaN devices offer superior switching speed, efficiency, and power density, the full exploitation of their capabilities is often hampered by conventional packaging technologies. This webinar explores advanced interconnect and heterogeneous integration technologies for GaN packaging in both RF and power applications. It will address top-side interconnects in chip-on-board GaN micro-assemblies, ultra-fine-pitch flip-chip techniques, and 3D die stacking, highlighting how these approaches reduce parasitic effects, improve thermal management, and enable highly integrated, high-power-density GaN systems.
About the Speaker:
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| Name / Surname | Ali ROSHANGHIAS |
Abhinay NALLAM |
Farough ROUSTAIE |
| Organisation / University | SAL Silicon Austria Labs GmbH |
Heraeus Electronics GmbH & Co. KG |
NanoWired GmbH |
| Title in the Organisation | Head of Research Unit for Heterogeneous Integration Technologies |
Testing Engineer |
Co-founder & Co-CEO |
| Role in ALL2GaN Project |
Leader in Work Package 4 "Integration and packaging of GaN devices" |
Development and qualification of packaging materials in GaN devices |
Development of die attach material and NanoWiring of wafers in Work Package 4 |
| Academic Background | Dr. Ali Roshanghias is the head of the research unit for heterogeneous integration technologies at Silicon Austria Labs (SAL). He received his Ph.D. in materials science and technology in 2012. He pursued his career as a post-doc researcher in Japan and Austria in the fields of electronic materials and advanced microelectronics packaging. In 2015 he joined SAL (formerly known as CTR Carinthian Tech Research AG). He is the author of more than 100 scientific papers and patents and serves as a lecturer at the University of Klagenfurt. |
Abhinay Nallam is a Testing Engineer at Heraeus Electronics GmbH & Co. KG, working in the Engineering Services and Testing Department since 2023. He completed his Bachelor's degree in Mechanical Engineering, India and subsequently pursued a Master's degree in Chemical and Energy Engineering at Otto von Guericke University Magdeburg, Germany. In 2021, he worked as a Research Assistant at Fraunhofer IWS, Dresden. He further strengthened his industrial expertise through his Internship and Master's Thesis at Robert Bosch GmbH in 2022. Alongside his professional role at Heraeus, he has been an active sub-group member of ECPE (European Center for Power Electronics) since 2023. |
Dr.-Ing. Farough Roustaie earned his degree (Dr.-Ing.) from TU Darmstadt, specializing in Microsystems Technology and Micro/Nano Systems. His research focused on the fabrication and integration of metallic nanostructures, field emission devices, and advanced interconnection technologies for microelectronics packaging. He has successfully transferred research results into industry as Co-Founder and Co-CEO of NanoWired GmbH. |
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| Why GaN? |
Although GaN devices offer superior switching speed, efficiency, and power density, the full exploitation of their capabilities is often hampered by conventional packaging technologies. This webinar explores advanced interconnect and heterogeneous integration technologies for GaN packaging in both RF and power applications. It will address top-side interconnects in chip-on-board GaN micro-assemblies, ultra-fine-pitch flip-chip techniques, and 3D die stacking, highlighting how these approaches reduce parasitic effects, improve thermal management, and enable highly integrated, high-power-density GaN systems. |
GaN offers much faster switching and lower power losses than silicon, enabling higher frequencies, smaller passives and higher power density at lower system cost. But GaN is a lateral device with all contacts on a thin top surface, so conventional power-module packaging does not apply. Unlocking GaN's performance is an interconnect and materials challenge. |
GaN enables higher efficiency, higher switching frequencies, and greater power density. NanoWired's room-temperature interconnection technology further enhances these benefits by reducing electrical resistance and inductance while minimizing thermal stress, allowing GaN devices to reach their full performance potential.
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| LinkedIn Profile |
https://www.linkedin.com/in/ali-roshanghias-ab04835b |
https://www.linkedin.com/in/abhinay-nallam-13a500112
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